The present invention relates to a semiconductor device, and more particularly, to failure analysis of semiconductor devices.
Large-volume semiconductor memory devices have been made depending upon advances in integration and scale-down of design rules. The same applies specifically to SRAM fabricating processes. The high integration may increase probability of making defective cells due to a short circuit or open circuit of SRAM cells, damage of SRAM cells, and the like. A conventional SRAM cell is shown in FIG. 1, including transistors T1-T6 arranged among wordline WL and bitlines BL and /BL. A procedure of developing semiconductor devices may necessitate securing stable manufacturing technology for scanning and reducing defects. For example, a failure analysis scheme has been utilized to secure stable manufacturing technology. According to the failure analysis scheme, it is possible to detect failure causes present in a semiconductor device under test and to improve the detected failure causes.
In particular, considering that methods of designing and manufacturing semiconductor devices are changed according to failure analysis results, an appropriate failure analysis scheme is very critical to developing semiconductor devices. For example, erroneous failure analysis causes delays in development due to many trials and errors. Conventional SRAM area-type failure analysis is made via EDS map testing, defect map testing, Test Element Group (TEG) testing, and the like.
In general, if transistors or interconnections in SRAM cells are defective, characteristic curves of defective SRAM cells may be different from a characteristic curve of a normal SRAM cell. That is, it is possible to analyze failure causes via characteristic curves. However, it is increasingly difficult to analyze failure causes due to advance in integration and/or complicated process technology.
Accordingly, speedy and exact failure analysis is very important to reduce delays in development and to improve time-to-market of semiconductor devices.